Business Wire

ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

SAN JOSE, Calif.--(BUSINESS WIRE)--April 4, 2005--ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) ...
EDN

Monterey adds Synplicity synthesis to ASIC design flow

SAN MATEO, Calif. — Claiming to have a full RTL-to-GDSII design flow at last, Monterey Design Systems has added logic synthesis to its Dolphin placement and routing system. The Dolphin-RTL synthesis ...
EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
Digi Times

PGC Integrates 2.5D/3D Advanced Packaging Technology to Break the Memory Wall and Accelerate AI/HPC ASIC Innovation

As AI models and computing demands continue to grow exponentially, the biggest challenge in chip design is no longer pure processing power, but the bandwidth gap between processors and memory. Even ...