Over the last ten years, we have seen tremendous progress in technologies for formal verification of the behavior of RTL designs. Today, these formal technologies are vastly more thorough than ...

Assertion-based verification (ABV) has recently emerged as the only functional verification methodology capable of keeping pace with increasingly complex integrated circuits. When using ABV, designers ...

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous ...

Adding assertions early and throughout the ASIC design cycle is the best way to independently check that design code reflects the intended behavior as specified in design specifications and the ...

Standardization work is underway to develop assertion languages (for example, PSL and SystemVerilog Assertions) to address the shortcomings of natural language specification. The goal in creating ...

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification ...

When unit tests fail, they should clearly explain why. Take advantage of the Fluent Assertions library to write unit test methods that are simple, readable, concise, and expressive. Unit testing is an ...