EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
Embedded

Moving from FPGA to ASIC for your AI chip? Here’s what you should know

Perhaps you are designing an embedded inference engine for edge computing. Or you are taking the next step in automotive vision processing. Or maybe you have an insight that can challenge Nvidia and ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
EDN

ASIC-FPGA high wire act

Remember when ASIC was ASIC and FPGA was an afterthought? It wasn't that long ago–maybe 10 years–but technology and market forces have done a lot to blur the distinction. Where there had been a clear ...
Digi Times

FPGA vs ASIC: Altera CEO highlights FPGA's advantage in AI era

Embedded World 2025 officially commenced this week in Nuremberg, Germany, with Sandra Rivera, CEO of FPGA company Altera, delivering the keynote address. In her presentation, Rivera discussed key ...
Business Wire

Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its FPGA-Go-ASIC™ prototyping platform solution. This ...
Electronic Design

FPGAs, Structured ASICs Bring Home The Bacon

FPGAs and structured ASICs are like Baby Boomers. They continue to look for ways to improve their position in life while reaping nice raises every year (in the form of revenue boosts). They're also ...
Electronic Design

Structured ASICs

So what’s a STRUCTURED ASIC? A Structured ASIC is a type of integrated circuit that contains blocks of logic, called "tiles." These tiles reside in the die ready to be connected in a customizable ...
VentureBeat

FPGA chips are coming on fast in the race to accelerate AI

AI is hungry, hyperscale AI ravenous. Both can devour processing, electricity, algorithms, and programming schedules. As AI models rapidly get larger and more complex (an estimated 10x a year), a ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design News

Is Platypus from Zero ASIC the FPGA equivalent to RISC-V?

Before I tell you what I’m about to tell you, let’s first refresh our minds as to RISC-V processors. Why? Well, because even though what I’m about to tell you has nothing to do with RISC-V per se, in ...