Design-Reuse

SpringSoft Simplifies Verification of Low-power Chips with Advanced Power-aware Debug Solution

New Verdi Power-aware Debug Module enables visualization of power intent with RTL and UPF/CPF for automated debug and analysis HSINCHU, Taiwan, February 8, 2010 - SpringSoft, Inc. (TAIEX: 2473), a ...
EDN

FPGA debugging techniques to speed up pre-silicon validation

The increase in complexity of designs being prototyped on FPGAs has led to the increase in need for better debugging techniques. The design being prototyped on the FPGA may be used for performing ...
EDN

How SLEC improves functional verification

Design teams commonly use system models for verification. System models have many advantages over register transfer level (RTL) code for verification, notably, because of their ease of development and ...
Business Wire

CM Engineering Standardizes on SpringSoft’s Verdi Debug in Advanced Chip Verification Environment

YOKOHAMA, Japan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, today announced that CM Engineering Co. Ltd. (CM Engineering) has adopted the Verdi™ Automated ...
Business Wire

SpringSoft, Vennsa Technologies Join Forces to Increase Verification Productivity with Interoperable Chip Debug and Analysis Solutions

As an integrated ecosystem, the Verdi and OnPoint products offer design and verification engineers a unified push-button flow for functional debugging, root cause analysis and design navigation. The ...
Semiconductor Engineering

Is Verification Falling Behind?

It’s becoming harder for tools and methodologies to keep up with increasing design complexity. How to prevent your design from being compromised. Every year that is in effect means that the ...
Semiconductor Engineering

Functional Safety Verification For AV SoC Designs Accelerated With Advanced Tools

Autonomous vehicles (AVs) will be the culmination of dozens of highly complex systems, incorporating state-of-the-art technologies in electronics hardware, sensors, software, and more. Conceiving and ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Design-Reuse

Hua Hong NEC Deploys Springsoft's Laker IC Design and Verdi Debug to Accelerate PDK Development and Chip Verification

HSINCHU, Taiwan, January 10, 2012 — SpringSoft, Inc., a global supplier of specialized IC design software, and Shanghai Hua Hong NEC Electronics Company, Ltd. (†Hua Hong NEC†), one of the ...
Embedded

Dealing with SoC hardware/software design complexity with scalable verification methods

The problem with today's existing methodologies is that verification issubservient to design. This principle requires a shift in paradigm,especially in designing complex electronic systems. Why?
Electronic Design

11 Myths About Using Formal Verification

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...