Design-Reuse

Achieving Compliance and Interoperability for Your PCI Express Design

Integrating PCI Express into a design requires verifying that the product is compliant to the PCI Express specification and interoperable with other PCI Express devices. To lower integration risk and ...
EDN

PCI Express Endpoint-DMA Initiator Subsystem

This application note demonstrates several key features of the Vivado Design Suite and the IP cores used in the design. The key features that are illustrated by this design include: Each of these ...
Design-Reuse

PCI-SIG DevCon 2013: M-PCIe with M-PHY Shifts into GEAR 3

In my last post, I discussed highlights from the recent 2013 PCI-SIG Developer’s Conference including PCIe 4.0, OCuLink and M-PCIe. I also provided information on the world’s first M-PCIe ...
EDN

Using PCI Express as the Primary System Interconnect

With the benefits of reduced power consumption, scalability of bandwidth, increased data throughput and improved signal integrity, PCI Express (PCIe®) has replaced legacy bus-based PCI and PCI-X, and ...
Semiconductor Engineering

Connecting Emulated Designs To Real PCIe Devices

These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary ...
Electronic Design

What’s the Difference Between the Palladium Emulator and an FPGA for PCIe Debug?

PCI-SIG’s Peripheral Component Interconnect Express Gen5 (PCIe Gen5) is a system protocol used primarily for data transfers at high rates in systems. A transfer rate of 32 Gb/s can be achieved by PCIe ...